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STE45NK80ZD
N-CHANNEL 800V - 0.11 - 45 A ISOTOP Super FREDMeshTM MOSFET
Table 1: General Features
TYPE STE45NK80ZD
s s s s s s
Figure 1: Package
ID 45 A Pw 600 W
VDSS 800 V
RDS(on) < 0.13
TYPICAL RDS(on) = 0.11 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY
ISOTOP
DESCRIPTION The SuperFREDMeshTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
Figure 2: Internal Schematic Diagram
APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR WELDING EQUIPMENT
Table 2: Order Codes
SALES TYPE STE45NK80ZD MARKING E45NK80ZD PACKAGE ISOTOP PACKAGING TUBE
Rev. 6 April 2005 1/10
www..com
STE45NK80ZD
Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID IDM (*) PTOT PTOT Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C (Steady State) Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C (Steady State) Derating Factor Gate source ESD(HBM-C=100pF, R=1.5k) Peak Diode Recovery voltage slope Insulation Withstand Voltage (AC-RMS) from All Four Terminals to External Heatsink Operating Junction Temperature Storage Temperature Value 800 800 30 45 28 180 600 5 7 8 2500 Unit V V V A A A W W/C KV V/ns V
VESD(G-S)
dv/dt (1) VISO Tj Tstg
- 65 to 150
C
(*) Pulse width limited by safe operating area
(1) ISD 45A, di/dt 500 A/s, VDD V(BR)DSS.
Table 4: Thermal Data
Rthj-case Rthj-amb Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 0.2 40 C/W C/W
Table 5: Avalanche Characteristics
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 35 V) Max. Value 45 1.2 Unit A J
Table 6: Gate-Source Zener Diode
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 150A VGS = 10V, ID = 22.5 A 2.5 3.75 0.11 Min. 800 10 100 10 4.5 0.13 Typ. Max. Unit V A A A V
Table 8: Dynamic
Symbol gfs (1) Ciss Coss Crss Coss eq. (3) td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15V, ID = 22.5 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 35 26000 1620 260 700 105 128 350 174 558 121 307 781 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
VGS = 0V, VDS = 0V to 720V VDD = 400 V, ID = 20 A RG = 4.7 ,VGS = 10 V (see Figure 17) VDD = 400 V, ID = 40 A, VGS = 10V
Table 9: Source Drain Diode
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 45 A, VGS = 0 ISD = 40 A, di/dt = 100A/s VDD = 50 V, Tj = 25C (see Figure 18) ISD = 40 A, di/dt = 100A/s VDD = 50 V, Tj = 150C (see Figure 18) 375 4.65 24.8 568 9.66 34 Test Conditions Min. Typ. Max. 45 180 1.6 Unit A A V ns C A ns C A
(1) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. (3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized BVdss vs Temperature
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Figure 15: Avalanche Energy vs Starting Tj
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Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform
Figure 17: Switching Times Test Circuit For Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
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ISOTOP MECHANICAL DATA
DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248
G O B
A
N
D
E
J K L M
H
C
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F
STE45NK80ZD
Table 10: Revision History
Date 05-Jul-2004 15-Oct-2004 04-Nov-2004 09-Dec-2004 14-Dec-2004 05-Apr-2055 Revision 1 2 3 4 5 6 Description of Changes First Release. New value inserted in table 3. (VISO ) Preliminary Status Final datasheet Modified note 1 in table3. Modified figure 12
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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